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DS2176 t1 receive buffer DS2176 022798 1/14 features ? synchronizes looptimed and systemtimed t1 data streams ? twoframe buffer depth; slips occur on frame bound- aries ? output indicates when slip occurs ? buffer may be recentered externally ? ideal for 1.544 to 2.048 mhz rate conversion ? interfaces to parallel or serial backplanes ? extracts and buffers robbedbit signalling ? inhibits signalling updates during alarm or slip condi- tions ? integration feature adebounceso signalling ? slipcompensated output indicates when signalling updates occur ? compatible with ds2180a t1 transceiver ? surface mount package available, designated DS2176q ? industrial temperature range of 40 c to +85 c avail- able, designated DS2176n pin assignment sigh slip aln s/p 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vdd sclksel sysclk sser sbit8 smsync sigfrz sfsync fms rmsync rclk rser a b c d schclk sm0 sm1 vss rser rclk rmsync sigh vdd sclksel sysclk sser slip sbit8 nc nc smsync sigfrz sm0 sm1 vss s/p fms aln sfsync a b nc nc c d schclk 24pin 300 mil dip 28pin plcc description the DS2176 is a lowpower cmos device specifically designed for synchronizing receive side looptimed t carrier data streams with system side timing. the de- vice has several flexible operating modes which simplify interfacing incoming data to parallel and serial tdm backplanes. the device extracts, buffers and integrates abcd signalling; signalling updates are prohibited dur- ing alarm or slip conditions. the buffer replaces exten- sive hardware in existing applications with one askinnyo 24lead package. application areas include digital trunks, drop and insert equipment, transcoders, digital crossconnects (dacs), private network equipment and pabxtocomputer interfaces such as dmi and cpi.
DS2176 022798 2/14 DS2176 block diagram figure 1 slip sigh aln v ss v dd s/p pcm buffer slip logic system controller receive controller rser rclk rmsync sser sfsync sbit8 smsync schclk sclksel sysclk sigfrz a b c d fms sm0 sm1 signalling buffer
DS2176 022798 3/14 pin description table 1 pin symbol type description 1 sigh i signalling inhibit . when low, abcd signalling updates are disabled for a period determined by sm0 and sm1, or until returned high. 2 rmsync i receive multiframe sync . must be pulsed high at multiframe boundaries to establish frame and multiframe alignment. 3 rclk i receive clock . primary 1.544 mhz clock. 4 rser i receive serial data . sampled on falling edge of rclk. 5 6 a b o robbedbit signalling outputs 6 7 b c 7 8 c d 9 schclk o system channel clock . transitions high on channel boundaries; useful for serial to parallel conversion of channel data. 10 sm0 i signalling modes 0 and 1 . select signalling supervision technique. 11 sm1 gg ggp q 12 v ss signal ground . 0.0 volts. 13 s/p i serial/parallel select . tie to v ss for parallel backplane applications, to v dd for serial. 14 fms i frame mode select . tie to v ss to select 193s (d4) framing to v dd for 193e (extended). 15 aln i align . recenters buffer on next system side frame boundary when forced low. 16 sfsync i system frame sync . rising edge establishes start of frame. 17 sigfrz o signalling freeze . when high, indicates signalling updates have been dis- abled internally via a slip or externally by forcing sigh low. 18 smsync o system multiframe sync . slipcompensated multiframe output; indicates when signalling updates are made. 19 sbit8 o system bit 8 . high during the lsb time of each channel. used to reinsert extracted signalling into outgoing data stream. 20 slip o frame slip . active low, open collector output. held low for 65 sysclk cycles when a slip occurs. 21 sser o system serial out . updated on rising edge of sysclk. 22 sysclk i system clock . 1.544 or 2.048 mhz data clock. 23 sclksel i system clock select . tie to v ss for 1.544 mhz applications, to v dd for 2.048 mhz. 24 v dd positive supply . 5.0 volts.
DS2176 022798 4/14 overview the DS2176 performs two primary functions: 1) syn- chronization of received t1 pcm data (looped timed) to host backplane frequencies; 2) supervision of robbed bit signalling data embedded in the data stream. the buffer, while optimized for use with the ds2180a t1 transceiver, is also compatible with other transceiver devices. the ds2180a data sheet should serve as a valuable reference when designing with the DS2176. receive side timing figure 2 rclk rmsync rser lsb msb lsb f msb lsb channel 24 channel 1 data synchronization pcm buffer the DS2176 utilizes a 2frame buffer (386 bits) to syn- chronize incoming pcm data to the system backplane clock. the buffer samples data at rser on the falling edge of rclk. output data appears at sser and is up- dated on the rising edge of sysclk. a rising edge at rmsync establishes receive side frame and multi- frame alignment. a rising edge at sfsync establishes system side frame alignment. the buffer depth is constantly monitored by onboard contention logic; a aslipo occurs when the buffer is completely emptied or filled. slips automatically recenter the buffer to a one frame depth and always occur on frame boundaries. slip correction capability the 2frame buffer depth is adequate for most tcarrier applications where shortterm jitter synchronization, rather than correction of significant frequency differ- ences, is required. the DS2176 provides an ideal bal- ance between total delay and slip correction capability. buffer recentering many applications require that the buffer be recentered during system powerup and/or initialization. forcing aln low recenters the buffer on the occurrence of the next frame sync boundary. a slip will occur during this recentering if the buffer depth is adjusted. if the depth is presently optimum, no adjustment (slip) occurs. slip is held low for 65 sysclk cycles when a slip occurs. slip is an activelow, open collector output. buffer depth monitoring smsync is a system side output pulse which indicates system side multiframe boundaries. the distance be- tween rising edges at rmsync and smsync indi- cates the current buffer depth. slip direction and/or an impending slip condition may be determined by monitor- ing rmsync and smsync real time. smsync is held high for 65 sysclk cycles. clock select the device is compatible with two common backplane frequencies: 1.544 mhz, selected when sclksel=0; and 2.048 mhz, selected when sclksel=1. in 1.544 mhz applications the fbit is passed through the re- ceive buffer and presented at sser immediately after the rising edge of the system side frame sync. the fbit is dropped in 2.048 mhz applications and the msb of channel 1 appears at sser one bit period after a rising edge at sfsync. sser is forced to 1 in all channels greater than 24. see figures 3 and 4. in 2.048 mhz applications (sclksel=1), the pcm buffer control logic establishes slip criteria different from that used in 1.544 mhz applications to compensate for the faster systemside read frequency. parallel compatibility the DS2176 is compatible with parallel and serial back- planes. channel 1 data appears at sser after a rising edge at sfsync as shown in figures 3 and 4 (serial ap- plications, s/p =1). the device utilizes a lookahead cir- cuit in parallel applications (s/p =0). data is output 8 clocks earlier, allowing the user to convert parallel data externally.
sysclk msb lsb channel 1 msb lsb msb lsb channel 1 channel 2 sfsync smsync schclk sser (s/p =0) sser (s/p =1) sbit8 channel 1 a, b, c, d forced to 1 in channels 25 thru 32 forced to 1 in channels 25 thru 32 DS2176 022798 5/14 system multiframe boundary timing (sysclk = 1.544 mhz) figure 3 sysclk lsb msb lsb f msb lsb channel 24 channel 1 lsb msb lsb f msb lsb channel 1 channel 2 sfsync smsync schclk sser (s/p =0) sser (s/p =1) sbit8 channel 24 channel 1 a, b, c, d system multiframe boundary timing (sysclk = 2.048 mhz) figure 4
DS2176 022798 6/14 193s system multiframe timing figure 5 frame# 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 sfsync smsync 193e system multiframe timing figure 6 frame# 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 sfsync smsync signalling supervision extraction in digital channel banks, robbedbit signalling data is in- serted into the lsb position of each channel during sig- nalling frames. in 193s framing (fms=0) applications, a signalling data is inserted into frame 6 and b signalling data is inserted into frame 12. 193e framing (fms=1) includes two additional signalling bits: c signalling is in- serted into frame 18 and d signalling is inserted into frame 24. this embedded signalling data is synchro- nized to system side timing (via the pcm buffer) before being extracted and presented at outputs a, b, c, and d. outputs a, b, c, and d are valid for each individual channel time and are repeated per channel for all frames of the multiframe. in 193s applications, outputs c and d contain the previous multiframe's a and b data. signalling updates occur once per multiframe at the ris- ing edge of smsync unless prohibited by a freeze. freeze the signalling buffer allows the DS2176 to afreezeo (pre- vent update of) signalling information during alarm or slip conditions. a slip condition or forcing sigh low freezes signalling; duration of the freeze is dependent on sm0 and sm1. updates will be unconditionally pro- hibited when sigh is held low. during freezing condi- tions aoldo data is recirculated in the output registers and appears at a, b, c and d. sigfrz is held high during the freeze condition, and returns low on the next signal- ling update. input to output delay of signalling data is equal to 1 multiframe (the depth of the signalling buffer) + the current depth of the pcm buffer (1 frame approxi- mately 1 frame). integration signalling integration is another feature of the DS2176; when selected, it minimizes the impact of random noise hits on the span and resultant robbedbit signalling cor- ruption. integration requires that perchannel signalling data be in the same state for two or more multiframes before appearing at a, b, c and d. sm0 and sm1 are used to select the degree of integration or to totally by- pass the feature. integration is limited to two multi- frames during slip or alarm conditions to minimize up- date delay. clear channel considerations the DS2176 does not merge the aprocessedo signalling information with outgoing pcm data at sser; this as- sures integrity of data in clear channel applications. sbit8 indicates the lsb position of each channel; when combined with offchip support logic, it allows the user to selectively reinsert robbedbit signalling data into the outgoing data stream.
DS2176 022798 7/14 signalling supervision modes table 2 sm0 sm1 fms selected mode 0 0 0 193s framing, no integration, 1 multiframe freeze. 0 0 1 193e framing, no integration, 1 multiframe freeze. 0 1 0 193s framing, 2 multiframes integration and freeze. 0 1 1 193e framing, 2 multiframes integration and freeze. 1 0 0 1 193s framing, 5 multiframes integration, 2 multiframes freeze. 1 0 1 1 193e framing, 3 multiframes integration, 2 multiframes freeze 1 1 0 193s framing, no integration, 1 multiframe freeze, replace robbed bit signal- ing bits at sser with ones. 1 1 1 193e framing, no integration, 1 multiframe freeze, replace robbed bit signal- ling bits at sser with ones. note: 1. during slip or alarm conditions, integration is limited to two multiframes to minimize signalling delay. slip and signalling supervision logic timing figure 7 sigfrz 1 sigh aln 2 smsync slip notes: 1. integration feature disabled (sm0=sm1=0) in timing set shown. 2. depending on present buffer depth, forcing aln low may or may not cause a slip condition.
DS2176 022798 8/14 DS2176/ds2180a system application figure 8 shows how the ds2180a t1 transceiver and DS2176 receive buffer interconnect in a typical ap- plication. serial 1.544 mhz backplane interface figure 8 rst int s/p aln sigh slip transmit line interface ds2186 receive line interface ds2187 transmit backplane interface control pcm signalling 1.544 mhz serial backplane data link supervision host controller ds2180a DS2176 tpos tneg rpos rneg vdd sps rlclk tlclk rlink tlink tmsync test vss tsigsel tsigfr tchclk tabcd tser tclk tmo tfsync rclk rmsync rser rfer rlos sdi sclk cs sdo rclk rmsync rser sm0 sm1 fms sclksel vss vdd a b c d sser sysclk sfsync smsync
DS2176 022798 9/14 absolute maximum ratings* voltage on any pin relative to ground 1.0v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v dd +0.3 v logic 0 v il 0.3 +0.8 v supply v dd 4.5 5.5 v dc electrical characteristics (0 c to 70 c; v dd =5v 10%) parameter symbol min typ max units notes supply current i dd 5 10 ma 1, 2 input leakage i il 1.0 +1.0 m a output current @ 2.4v i oh 1.0 ma 3 output current @ 0.4v i ol +4.0 ma 4 output leakage i lo 1.0 +1.0 m a 5 notes: 1. tclk=rclk=1.544 mhz. 2. outputs open. 3. all outputs except slip , which is open collector. 4. all outputs. 5. applies to slip when tristated. capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf
DS2176 022798 10/14 ac electrical characteristics (0 c to 70 c; v dd =5v 10%) parameter symbol min typ max units notes rclk period t rclk 250 648 ns rclk, sysclk rise and fall times t r , t f 20 ns rclk pulse width t rwh , t rwl 125 324 ns sysclk pulse width t swh , t swl 100 244 ns sysclk period t sysclk 200 488 ns rmsync setup to rclk falling t sc 20 t rwh 5 ns sfsync setup to sysclk falling t sc 20 t swh 5 ns rmsync, sfsync, sigh , aln pulse width t pw 50 ns rser setup to rclk falling t sd 50 ns rser hold from rclk falling t hd 50 ns propagation delay sysclk to sser, a, b, c, d t pvd 100 ns propagation delay sysclk to smsync high t pss 75 ns propagation delay sysclk or rclk to slip low t ps 100 ns propagation delay sysclk to sigfrz low/high t psf 75 ns aln , sigh setup to sfsync rising t sr 500 ns notes: 1. measured at v ih =2.0v, v il =0.8v, and 10 ns maximum rise and fall times. 2. output load capacitance = 100 pf.
aln , sigh slip t r t f t sysclk t swh t swl t sc t pw t pvd t ps sysclk sfsync sser t pss t pw t sr sbit8, t psf sigfrz a, b, c, d smsync schclk, DS2176 022798 11/14 receive ac diagram figure 9 slip t r t f t rclk t rwh t rwl t s t pw t pvd t ps t sd t hd rclk rmsync rser system ac timing diagram figure 10
DS2176 022798 12/14 DS2176 t1 receive buffer a b j 11 equal spaces at .100 .010 (tna) kg c e f d h dim min max 24pin pkg a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.245 1.265 0.250 0.270 0.125 0.145 0.300 0.325 0.015 0.040 0.125 0.135 0.090 0.110 0.325 0.420 0.008 0.012 0.015 0.022
DS2176 022798 13/14 DS2176q ch1 n 1 e e1 d1 d d2 e2 e1 c a1 a2 a b l1 b1 inches dim min max a 0.165 0.180 a1 0.090 0.120 a2 0.020 b 0.026 0.033 b1 0.013 0.021 c 0.009 0.012 d 0.485 0.495 d1 0.450 0.456 d2 0.390 0.430 e 0.485 0.495 e1 0.450 0.456 e2 0.390 0.430 l1 0.060 n 28 e1 0.050 bsc ch1 0.042 0.048
DS2176 022798 14/14 data sheet revision summary the following represent the key differences between 04/19/95 and 06/13/97 version of the DS2176 data sheet. please review this summary carefully. 1. sync/clock relationship in timing diagram

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